When the wiring of a semiconductor device is formed, first a barrier layer and a conductor layer are successively formed on an insulator layer having trenches. Then, at least portion of the conductor layer located outside of the trenches (outside portion of the conductor layer) and portion of the barrier layer located outside of the trenches (outside portion of the barrier layer) are removed by chemical mechanical polishing. Such polishing to remove at least the outside portion of the conductor layer and the outside portion of the barrier layer is generally carried out as two steps: a first polishing step and a second polishing step. In the first polishing step, part of the outside portion of the conductor layer is removed to expose the upper surface of the barrier layer. Removal of part of the outside portion of the conductor layer is generally begun at what is initially a relatively high polishing removal rate, after which the polishing removal rate is held down in order to minimize the formation of steps between the upper surface of the conductor layer and the upper surface of the barrier layer. In the subsequent second polishing step, at least the remainder of the outside portion of the conductor layer and the outside portion of the barrier layer (in some cases, part of the insulator layer as well) are removed in order to expose the insulator layer and obtain a flat surface. Conductor wiring composed of the portions of the conductor layer remaining within the trenches is thereby obtained.
In such polishing for the purpose of forming the wiring of a semiconductor device, particularly polishing in the second polishing step, use is generally made of a polishing composition that includes both a polishing accelerator such as an acid and an oxidizing agent and further includes, where necessary, polishing abrasive grains. It has been proposed that an organic acid and a surfactant be added to a polishing composition to increase the polishing removal rate and reduce defects in an object to be polished after polishing. For example, Patent Document 1 discloses a polishing composition containing two types of abrasive grains of different sizes, a triazole compound, and an organic acid such as PBTC, and attempts both to increase the barrier layer polishing removal rate and to suppress defects such as surface contamination. Patent Document 2 discloses a polishing composition containing a metal oxide dissolving agent, abrasive grains, and a surfactant such as HEDP that keeps the abrasive grains from precipitating. The aim of using a surfactant that keeps the abrasive grains from precipitating is both to increase the ease of cleaning an object to be polished and to reduce the adhesion of foreign matter to the object to be polished. Patent Document 3 discloses a polishing composition containing an oxidizing agent and a specific compound of HEDP or NTMP. The prime aim of using the specific compound is to form a metal protective film on an object to be polished composed of copper or silver to reduce defects such as corrosion on the object to be polished.
However, when the wiring of a semiconductor device is formed by chemical mechanical polishing, scratches commonly appear on the conductor wiring. Reducing such scratches to a satisfactory level with the polishing compositions disclosed in Patent Documents 1-3 is difficult.
One cause of scratches on conductor wiring is thought to be aggregation of abrasive grains in a polishing composition. Means that have been adopted for reducing such scratching include, for example, removing coarse abrasive grains from the polishing composition, preventing abrasive grains aggregation within the composition, and adding a chemical substance having the effect of forming a protective film on the surface of the conductor layer. However, such means do not sufficiently reduce scratching.
In another means for reducing scratching, a new problem sometimes arises. Specifically, portions of a conductor layer that are located in trenches and are not supposed to be removed end up being removed by polishing more rapidly than an insulator layer, which results in the increase of the size of steps between the upper surface of the conductor wiring and the upper surface of the insulator layer.